Electro-optical display panel with control transistors and method for making it

ABSTRACT

The invention concerns an electro-optical panel and, more especially, an intersection point transistor structure made with thin films, wherein there is provided a doubling of the line and column electrodes (LG, CL) by doubling elements (1g 1 , Col. 1, Col. 2), as well as a light barrier (EC) shielding a transistor. The invention also concerns a method for making a screen of this type. The invention can be applied especially in the technology of liquid crystal display panels.

The invention concerns an electro-optical display panel with controltransistors and, more particularly, a flat panel in which each pixel tobe displayed is controlled by a transistor. It can be applied to themaking of large-area liquid crystal flat panels, the control transistorsof which are made by integration in the form of thin layers. The methodaccording to the invention enables the making of a panel by a redundantmethod with a minimum number of lithographic masks.

As is known, these panels generally have a large number of elementarypoints or pixels which are square-shaped or rectangular. These pixelsshould be addressed individually. The definition of the panel depends onthe number of point capable of receiving a piece of information. Eachpoint is controlled by applying an electrical field through the liquidcrystal. To display alphanumerical or graphic data, matrix-type displayshave been proposed. Each pixel is then defined by the intersection oftwo networks of orthogonal conductors called lines and columns.

The addressing of these matrix display panels is becoming increasinglyimportant as it being sought to increase their definition, namely thenumber of pixels.

Since the pixels are addressed sequentially line by line, the number oflines that can be addressed is generally limited by the characteristicsof the electro-optical effect of the liquid crystal used. The differencein voltages that can be achieved in direct addressing between an lit-upstate and an off state, by placing the line and column voltages in phaseor in phase opposition, diminishes with the number of lines. Thepossibility of addressing a large number of lines (<100) then arises tothe detriment of the other characteristics of the panel (diminishing ofcontrast and an ever increasing variation in contrast with the visualangle). To improve the performance of these panels, a transistor or anon-linear element can be series connected with each pixel (forming acapacitor). The set then behaves like a memory element. A voltage ischarged when the transistor is unblocked by a line pulse. This voltageis maintained in the pixel for the rest of the time of the frame duringwhich the transistor is off.

At present, the requirements of display panel technology relate to ahigher definition of the image. In matrix display type panels, this thenleads to designing devices with a large number of addressing lines orcolumns. Their number can go up to 1024 or even more. Thiscorrespondingly increases the number of control transistors. For seriesmanufacturing, it is necessary especially to obtain high output, goodreproducibility and high stability for these components. It is furthernecessary to adapt, also with good reproducibility, the electricalcharacteristics of the component to that of the associated cell.

A presently common method of resolving this problem and of improving theperformance of these panels consists in doing this addressing operationby means of a matrix of transistors in thin films: this amounts todirectly coupling the electro-optical effect to a giant, butlow-resolution "integrated circuit" responsible for performing the datashunting and memorizing functions.

This approach definitely entails technological difficulties both in themaking of thin film transistors and as regards the interconnectionconductors. In particular, it is imperative that, among the very largenumber of intersections between the lines and columns of theinterconnection system, no intersection should be defective.

For, according to a usual technique, the transistors are located at thepoints of intersection of line conductors and column conductors whichare insulated from each other in such a way that an appropriatepotential difference, applied between a line and a column, determineswhether the transistor connected between this line, this column and theadjacent pixel is on or off.

The present invention relates to display panels comprising a layer ofelectro-optical material controlled by an integrated matrix oftransistors. This invention describes the manufacturing method of apanel of this type. The current technologies use 2 or 3 levels ofmasking with transistors gate side up, and 4 to 5 levels of maskings fortransistors gate side down. But technologies of this type suffer from alack of flexibility when it is sought to improve the image by a storagecapacity or a light barrier.

The following method can be used to build a very sophisticated panel(light barrier and storage capacity) in six levels of masking, butcombine the technological advantages achieved with seven or nine levelsof maskings. These advantages are redundancy in lines and columns whichare doubled to avoid breaks, double insulation at the intersection ofthe lines and columns with a silicon pad, if necessary, as areinforcement. There is no additional etching which is not essential torelease the outward connections of the lines and columns. Theconnections of the lines and columns can be of the same nature. Thepixel can be insulated with ITO (indium tin oxide) between the twolayers of insulants, thus reducing the number of false points throughshort circuits with the line or the column. Or else a storage capacitycan be made between the previous line and the pixel with a double layerof insulants to prevent short circuits. Finally, this technology usestransistors, gate side down, where the aging of the transistors isimproved both at the level of the channel and at that of the contacts.

The invention therefore relates to an electro-optical display panel withcontrol transistors comprising:

a first strip and a second strip which are parallel and which enclose anelectro-optical material;

the first strip being provided on its surface, in contact with theelectro-optical material, with a matrix of pixels arranged in lines andcolumns, line control electrodes at a rate of one electrode associatedwith each line of pixels of said matrix and placed parallel to each lineof pixels, and control transistors at a rate of one transistor per pixelcoupling this pixel to said line control electrodes;

the second strip being provided, on its surface in contact with theelectro-optical material, with at least one electrode; characterized inthat each transistor comprises:

a gate placed on the surface of the first strip and associated with aline control electrode;

a first layer of insulating material covering the entire said face withthe line control electrodes and gates;

an element made of amorphous semi-conductive material overlapping thegate;

a source placed on this element made of amorphous semi-conductivematerial and extending from one edge of the gate towards a pixel;

a drain placed on said element made of amorphous semi-conductor materialand extending from another edge of the gate towards a column electrode;

a second layer of insulating material covering the entire panel on whichthe following elements are placed:

at least one pixel;

a first connection element crossing the second layer of insulant andconnecting the source to the pixel;

at least one column control electrode;

a second connecting element crossing the second layer of insulant andconnecting the drain to said column;

a light barrier placed above the gate.

The invention also concerns a method for making a liquid crystal displaypanel, characterized in that it comprises the following steps:

(a) a first step for making, on the surface of said first strip of linecontrol electrodes, gates connected to these line control electrodes andportions of column electrodes that do not cut the line electrodes.

(b) a second step for the sucessive making of a first layer of insulant,a layer of an amorphous semi-conducting material, a layer of a dopedsemi-conducting material and, if necessary, a metallic layer;

(c) a third step of making two etchings, in the layer of amorphoussemi-conductive material, of elements that each overlap a gate and, inthe layer of doped semi-conductive material and in the metallic layer,of a source and a drain leaving an unoccupied space above the gate andextending, as for the source, towards the location of a pixel and, asfor the drain, towards the location of a column electrode;

(d) a fourth step for the making of a second passivation insulant layer;

(e) a fifth step for the etching of cavities for the connection ofcontacts crossing the second layer of insulant at the location of thesources and drains, and cavities for the connection of contacts crossingthe first layer and second layer of insulant at the location of the lineand column electrodes;

(f) a sixth step for the depositing of a layer of a conductive material;

(g) a seventh step for the etching of pixels in this conductive layer;

(h) an eighth layer for the depositing of a metallic layer;

(i) a ninth step for the etching in this metallic layer:

of column control electrodes passing through the cavities for theconnection of contacts, thus enabling them to be connected to columnelectrodes;

portions of line electrodes passing through the cavities for theconnection of contacts (CX3) enabling them to be connected to linecontrol electrodes (LG);

connection elements connecting, firstly, a source to a column electrodeand, secondly, a drain to a pixel;

light barriers shielding the amorphous semi-conducting material on topof the gate from all incident light;

(j) a tenth step for finishing a panel comprising the followingoperations:

the depositing of a fixing layer;

the positioning of thickness shims;

the making of the counter-strip with a transparent counter-electrodecovered with a fixing strip;

the placing of a liquid crystal.

The various objects and features of the invention will appear moreclearly from the following description which is made with reference tothe appended figures, representing:

FIG. 1, a perspective view of an embodiment of a liquid crystal displaypanel according to the prior art;

FIG. 2, a general view of an embodiment of a liquid crystal displaypanel according to the invention;

FIGS. 3 to 12, different steps in the method for making the liquidcrystal display panel according to the invention;

FIGS. 13 to 14, an alternative embodiment of the liquid crystal displaypanel according to the invention;

FIGS. 15 and 16, another alternative ambodiment of the liquid crystaldisplay according to the invention;

FIGS. 17 to 19, other alternative embodiments of the liquid crystaldisplay panel according to the invention.

Referring to FIG. 1 we shall first decribe an example of a known liquidcrystal display panel such as the one described, for example, in theFrench patent application Nos. 85.12804 or 85.16935.

This figure shows, on a surface 10 of a first strip 1, the lineconductors LG1 and LG2, the column conductors CL1, CL2 and CL3.Connected substantially to each intersection point, there are alsotransistors and pixels such as the transistor T11 and the pixel PX11located at the intersection of the line conductor LG1 and the columnconductor CL1.

The second strip 1', preferably made of glass, provided with at leastone eletrode F, determines with one of its sides 10' and the side 10 ofthe strip 1, a space in which a liquid crystal CX is placed.

The strip 1' is transparent. A pixel of the surface 10 such as PX11, thestrip 1' which faces it and the liquid crystal which separate themconstitute a liquid crystal cell of the panel.

The working of a panel of this type is known. It may be simply recalledthat to display a piece of information on a liquid crystal cell,suitable potentials should be applied to a line (LG1 for example) and acolumn (CL1 for example) turning on the transistor T11 which thenapplies a potential to the pixel PX11 in such a way that the pixel PX11of the cell CL11 is subjected to a difference in potential enabling achange in the state of the liquid crystal.

Referring to FIGS. 2, 11 and 12 we shall describe an embodiment of adisplay panel according to the invention.

FIG. 2 shows a general view of a part of a liquid crystal display panel.FIG. 12 gives a more detailed view of an intersection point of the paneland FIG. 11 shows a sectional view along as of FIG. 12, where thestructure of a transistor of a point of intersection is seen moreclearly. We shall therefore refer more especially, in the followingdescription, to FIGS. 11 and 12 to describe a control transistor of thepanel, but for clearer understanding, reference can also be made to FIG.2 where the same references designate the same elements.

On the surface 10 of a substrate, there are placed line controlelectrodes such as LG, gates such GR and portions of column electrodesCol1, Col2. According to the embodiment shown in the figures, a gate GRconsists of a line electrode portion.

The gates GR and line electrodes are covered with a layer of insulatingmaterial such as Si₃ N₄. On this layer, on top of each grill, there isan element made of a non-doped semi-conducting material such asamorphous silicon.

To complete the control transistor, a source SO and a drain DR arelocated on the element 3 on either side of the gate. This source andthis conductor are made of doped semi-conductive material such as n⁺doped silicon coated with a metallic layer. The entire unit is coveredwith a passivation insulant layer 6 such as Si₃ N₄ or SiO₂.

On this insulating layer 6 there are made pixels PX as well as lightbarriers EC, column control electrodes and portions of line electrodessuch as 1g 1.

The light barriers EC each cover a surface greater than a drain/sourcespace so as to shield the non-doped semi-conductor from light.

Finally, connection elements complete the structure. It is thus that:

connection elements such as CSP cross the passivation insulant layer 6and each connect a source SO to a pixel PX;

connection elements such as CDC cross the passivation insulant layer 6and each connect a drain DR to a column control electrode;

connection elements such as CX3, CX4, CX5 cross both insulant layers 2and 6 and connect, firstly, the line electrode portions (1g 1) to theline control electrodes LG (this is the case for the element CX3) and,secondly, the column electrodes CL to the column electrode portions Col1, Col 2 (as is the case for the elements CX4, CX5).

According to an alternative embodiment of the panel of the invention, asshown in FIGS. 13 and 14, the pixels PX are shown located between thetwo layers 2 and 6 of insulating material. The insulant layer thenserves as a storage capacity for the panel. Furthermore, this enables areduction in the number of false points because the line electrodes andthe column electrodes are no longer at the same level as the pixels.

In this case each connecting element CSP, connecting source SO to apixel PX, crosses the insulant layer 6.

According to another embodiment shown in FIGS. 15 and 16 and derivedfrom that of FIGS. 13 and 14, each pixel PX is directly connected to asource SO.

According to another alternative embodiment, connecting elements whichare not shown connect the light barrier to the gate located at thebottom. Thus a double-gate transistor is got.

Another alternative embodiment according to the invention comprises, asshown in FIGS. 17 and 18, at least one indentation for the source SO insuch a way that this source is placed crosswise with respect to the gateGR, and at least another indentation for the drain DR, directed parallelto the source in such a way that the drain is also crosswise withrespect to the gate. An embodiment of this type gives the transistorwhich is geometrically constant for all variations in the positioning ofthe masks. A double indentation of the drain provides a gain in spaceand does away with the effect of variations in the width of the lines onthe unwanted capacitances of the TFT.

In the embodiment shown in FIGS. 17 and 18, the drain DR has twoindentations surrounding the source SO.

On top of the gate, overlapping the drain and the source, the lightbarrier shields the transistor from light. It must be noted that thetransistor is entirely protected by the gate GR from the light comingthrough the substrate 1.

Finally, according to another alternative shown in a simplified way inFIG. 19, the pixel PS has at least one identation which extends abovethe line electrode so as to constitute a storage capacity with theinsulant material located between this indentation and the lineelectrode. This storage capacity improves the holding time of thedisplay and improves the grey shades. Moreover, in giving thisindentation of the pixel a maximum width, this indentation mayconstitute an armour for the liquid crystal against the effects of thevoltage of the line electrode.

We shall now describe an example of a manufacturing method according tothe invention. FIGS. 3 to 12 illustrate different steps in this method.

During a first step, on the surface 10 of a substrate 1, such as a glassstrip, electrodes are made with a conductive material for the control ofthe lines LG, gates GR connected to these electrodes and portions ofcolumn electrodes Col 1, Col 2 called column reinforcements. Thus aconfiguration is obtained as shown in FIGS. 3 and 4 wherein, forexample, a gate GR is actually a part of a line controlled electrode LG.This manufacturing step is performed by depositing a thin metallic layeron a virgin substrate under the best possible temperature and cleaningconditions to obtain a metal with low resistivity and without holes andthen, by photolithography, by attack on the lines, transistor gates andcolumn reinforcements. This metal, which is chemically resistant likechromium, can be cleaned violently with acids.

During a second step, a layer 3 of an amorphous semi-conductor material,a layer of an n⁺ doped semi-conductive material, and if necessary, alayer 5 of a metallic material are made successively. For example, inthe same machine, a gate insulant, for example Si₃ N₄, a semi-conductor,for example non-doped amorphous silicon, a layer for ohmic contact, forexample a layer of n⁺ doped amorphous silicon, are depositedsuccessively in the same machine. All these layers will be made, forexample, by a plasma assisted heat decomposition method or else bysputtering. If necessary, a metal is deposited such as chrome in a verythin layer. This metal is subsequently used to improve selectivity whenattacking the gate and passivation insulants or else to shield theamorphous silicon beneath this layer.

During a third step, the metal and the n⁺ doped silicon are etched withsource SO and drain DR contact blocks in a second photolithographyoperation. A step of this kind is easy to adjust because the silicon isattacked on a very wide surface, thus enabling very precise detectionsat the end of the attack by dry method, the signal that is sent backbeing very big. The layer of non-doped semi-conductor can then be verythin and it is known that it then becomes far less photoconductive.

The non-doped silicon is etched in a third photolithography operationthat can be made very precise with respect to the insulant because avery thin, very uniform, non-doped and very extensive layer is etched.Thus a component such as the one shown in FIGS. 5 and 6 is got.

During a fourth step, an inorganic passivation insulant 6 such as Si₃ N₃or SiO₂ is deposited on the previous structure which is easy to cleanwith acid baths, with very small steps to be crossed for the passivationinsulant.

During a fifth step, this passivation insulant 6 and, at times, the gateinsulant 2 are etched in a fourth photolithographic operation. This thusenables the subsequent making of the necessary contacts at the output ofthe sources and drains of the transistors, needed at the outputs at theend of the lines and columns, by the metal of the lines and columns and,as the case may be, for connecting the light barrier to the gate.

In a sixth step, a conducting and possibly transparent layer, made ofdoped indium tin oxide (called ITO) is deposited. This deposit is etchedin a seventh step with pixels PX, contact blocks, doubled lines andcolumns or storage capacity with double insulant.

In an eighth step, a metal is deposited. This metal is etched in a ninthstep with columns, contacts on source and drain, source and pixelcontacts, doubling of lines and light barrier.

According to an alternative method of manufacture, there can beprovision, at this stage, for connecting the light barrier EC to thegate GR to make a double gate transistor.

According to this embodiment, the faults due to short circuits can becorrected. Since the intersection of lines and columns has doubleinsulation, and this is a definite advantage, most of the short circuitswill be localized on the transistor. It is therefore enough to cut theincomings at these transistors to insulate these major faults withouthaving to cut the line or the column (electronic costs). If necessary,the ends of the cut lines and columns will be connected to both ends. Itwill be noted that the light barrier on an insulant deposited on a smallstep is far better insulated than in the standard method usingself-aligned drains and columns.

The liquid crystal and the metallic lines and columns can be insulatedwithout any disadvantage by an organic polymer deposit which can beremoved by organic solvents, on the external contacts, once the cell issealed.

A tenth step for finishing the panel may be considered to be a standardone. It consists in the making of the counter-strip, colored filters ifnecessary, fixing layers on both strips (friction-treated polyimide,evaporation of SiO etc.), the sealing of the two strips filling withliquid crystal, removal of passivation polymers and of fixing polymers,if any, on the contacts.

According to an alternative manufacturing method according to theinvention, there is provision for making the PX pixels between the twoinsulant layers 2 and 6. For this purpose, according to this alternativemethod, the above-described sixth and seventh steps are made before thefourth step for depositing passivation insulant 6. Thus a structure isobtained such as the one described in FIGS. 13 or 14.

According to another alternative method derived from the above one andshown in FIGS. 15 and 16, the sixth and seventh steps being performedbefore the fourth step, there is provision, in the seventh step foretching pixels PX, for also etching the connection elements KC whichdirectly connect a source SO to a pixel PX. Furthermore, according tothis alternative, there is provision, in the second and third steps, formaking, firstly, the amorphous semi-conducting material element 3, andthen for making the layer of doped seme-conducting material 4 and themetallic layer 5 and then for etching these two last layers.

In these conditions, the amorphous semi-conducting material 3 is not incontact with the pixel PX.

Finally, according to another alternative method, the sixth and seventhsteps can be performed after the ninth step.

The invention can thus be used to obtain a panel and in which eachintersection point has double insulation and in which each pixel hashigh storage capacity.

It is clear that the above description has been given only as an exampleand that other alternatives can be considered without going beyond thescope of the invention.

I claim:
 1. An electro-optical display panel with control transistorscomprising:a first strip and a second strip (1, 1') which are paralleland which enclose an electro-optical material (CX); the first strip (1)being provided on its surface (10), in contact with the electro-opticalmaterial (CX), with a matrix of pixels (PX11 to PX22) arranged in linesand columns, line control electrodes (LG1, LG2) at a rate of oneelectrode associated with each line of pixels of said matrix and placedparallel to each line pixels, and control transistors (T11 to T22) at arate of one transistor per pixel (PX11 to PX22) coupling the pixel tosaid line control electrodes; the second strip (1') being provided, onits surface (10') in contact with the electro-optical material (CX),with at least one electrode (F); characterized in that each transistorcomprised: a gate (GR) placed on the surface (10) and associated with aline control electrode (LG); a first layer (2) of insulating materialcovering the entire surface (10) with the line control electrodes (LG)and the gates (GR); an element (3) made of amorphous semi-conductivematerial overlapping the gate (GR); a source (SO) placed on this element(3) made of amorphous semi-conductive material and extending from oneedge of the gate towards a pixel; a drain (DR) placed on said element(3) made of amorphous semi-conductor material and extending from anotheredge of the gate towards a column electrode; a second layer of insulantmaterial (6) covering the entire panel on which the following elementsare placed: at least one pixel (PX); a first connection element (CSP)crossing the second insulant layer (6) and connecting the source (SO) tothe pixel (PX); at least one column control electrode (CL); a secondconnecting element (CDC) crossing the second insulant layer (6) andconnecting the drain (DR) to said column control electrode; a lightbarrier (EC) placed above the gate.
 2. A panel according to claim 1characterized in that the light barrier (EC) is made of a metallicmaterial.
 3. A panel according to claim 1 characterized in that itcomprises, on the surface (10) of the first strip (1), duplicatedportions of column electrodes (Col 1, Col 2) interrupted in the vicinityof each control transistor and connected by connection elements (CX4,CX5), crossing the first and second insulant layers (2 and 6), to acolumn control electrode (CL).
 4. A panel according to claim 1characterized in that it comprises, on the second layer of insulantmaterial (6) duplicated portions of line electrodes (LG1) interrupted inthe vicinity of each transistor and connected by connection elements(CX3), crossing the first and second insulant layers (2 and 6) to a lineelectrode (LG).
 5. A panel according to claim 1 characterized in thateach pixel (PX) is located between the first and second layers ofinsulant material (2, 6).
 6. A panel according to claim 5 characterizedin that it comprises connection elements (CSP) crossing the secondinsulant layer (6) and connecting the source (SO) with a pixel (PX). 7.A panel according to claim 5 characterized in that each pixel has aconnection directly connecting the pixel (PX) to a source (SO).
 8. Apanel according to claim 1 characterized in that each element (3) madeof amorphous semi-conducting material is slightly compensated in boronto reduce its photoconductivity.
 9. A panel according to claim 1characterized in that:the element (3) made of amorphous semi-conductingmaterial covers a part of the gate (GR) so as to be completely shieldedfrom the light that reaches the substrate; the source (SO) comprises atleast one indentation crosswise with respect to the gate (GR) and theelement (3) made of semi-conducting material; the drain (DR) also has atleast one indentation parallel to the indentation of the source (SO);the light barrier (EC) is placed above the gate and the element (3) madeof semi-conductive material (3), thus overlapping the source and drainindentations.
 10. A panel according to claim 2 characterized in that thedrain (DR) comprises at least two indentations framing an indentation ofthe source (SO).
 11. A panel according to claim 1 characterized in thatthe pixel (PX) comprises an indentation which extends over the lineelectrode that controls it.
 12. A method for making a liquid crystaldisplay panel according to claim 1 characterized in that it comprisesthe following steps:a first step for making on a surface (10) of firststrip (1) of line control electrodes (LG), gates (GR) connected to theseline control electrodes (LG) and portions of column electrodes (Col 1,Col 2) that do not cut the line electrodes (LG). (b) a second step forthe successive making of a first insulant layer (2), a layer of anamorphous semi-conducting material (3), a layer of a dopedsemi-conducting material (4); (c) a third step of making two etchings,in the layer of amorphous semi-conductive material (3), of elements thateach overlap a gate (GR) and, in the layer of doped semi-conductingmaterial, of a source (SO) and a drain (DR) leaving an unoccupied spaceabove the gate and extending, as for the source (SO), towards thelocation of a pixel and, as for the drain (DR), towards the location ofa column electrode; (d) a fourth step for the making of a secondpassivation insulant layer (6); (e) a fifth step for the etching ofcavities (CX1, CX2) for the connection of contacts crossing the secondinsulant layer (6) at the location of the sources and drains, and ofcavities (CX3, CX4, CX5) for the connection of contacts crossing thefirst layer and second layer of insulant (2, 6) at the location of theline and column electrodes; (f) a sixth step for the depositing of alayer of a conductive material; (g) a seventh step for the etching ofpixels (PX) in this conductive layer; (h) an eighth step for thedepositing of a metallic layer over the layers on the surface; (i) aninth step for the etching in this metallic layer:of column controlelectrodes passing through the cavities for the connection of contacts(CX4, CX5), enabling them to be connected to portions of columnelectrodes (Col 1, Col 2); portions of line electrodes passing throughthe cavities for the connection of contacts (CX3) enabling them to beconnected to line control electrodes (LG); connection elementsconnecting, firstly, a source (SO) to column electrode and, secondly, adrain to a pixel; light barriers (EC) shielding the amorphoussemiconducting material on top of the gate from an incident light; (j) atenth step for finishing a panel comprising the following operations:thedepositing of a fixing layer; the positioning of thickness shims; themaking of the counter-strip with a transparent counter-electrode coveredwith a fixing strip; placing of a liquid crystal.
 13. A method accordingto claim 12 characterized in that the second step is completed by makinga layer of metal (5) and in that, during the third step, this layer isalso etched to make the source (SO) and drain (DR) contacts.
 14. Amethod according to claim 12 characterized in that the first stepcomprises a step for depositing a metallic layer on a surface (10) of asubstrate 1 followed by a stage for the etching by photolithography ofthe line control electrodes (LG), gates (GR) and column electrodeportions (Col 1, Col 2).
 15. A method according to claim 12characterized in that the insulant is Si₃ N₃.
 16. A method according toclaim 12 characterized in that the semi-conducting material is silicon.17. A method according to claim 12 characterized in that the second stepis performed by a plasma-assisted heat decomposition method or bysputtering.
 18. A method according to claim 12 characterized in that thesecond step comprises the making of a metallic layer (5) on the layer ofdoped semi-conducting material (4).
 19. A method according to claim 18characterized in that the third step comprises:a first stage for theetching of the metallic layer (5) and the layer of doped semi-conductingmaterial (4); a second stage for the etching of the layer of amorphoussemi-conducting material (3).
 20. A method according to claim 12characterized in that the third, the fifth and the seventh steps areperformed by photolithography.
 21. A method according to claim 12characterized in that in the sequence of step the sixth and seventhsteps precede the fifth step.
 22. A method according to claim 12characterized in that the sixth and seventh steps precede the fourthstep.
 23. A method according to claim 22 characterized in that theseventh step provides for the etching of the connection elements (CSP)of the pixels with the sources and in that the ninth step then does notprovide for the making of the connection elements of the pixels with thesources.
 24. A method according to claim 12 characterized in that thesixth and the seventh steps are performed after the ninth step.